Programmable Quasi Cyclic LDPC Encoder Architecture

Reduced Complexity Quasi-cyclic Ldpc Encoder for Ieee 802.11n

In this paper, we present a low complexity Quasi-cyclic -low-density-parity-check (QC-LDPC) encoder hardware based on Richardson and Urbanke lowertriangular algorithm for IEEE 802.11n wireless LAN Standard for 648 block length and 1/2 code rate. The LDPC encoder hardware implementation works at 301.433MHz and it can process 12.12 Gbps throughput. We apply the concept of multiplication by consta...

Low Complexity Quasi-Cyclic LDPC Decoder Architecture for IEEE 802.11n

In this paper, we present a fully pipelined LDPC decoder for 802.11n standard that supports variable block sizes and multiple code rates. The proposed architecture utilizes features of Quasi-Cyclic LDPC codes and layered decoding to reduce memory bits and interconnection complexity through efficient utilization of permutation network for forward and backward interconnection routing. Permutation...

A Memory Efficient FPGA Implementation of Quasi-Cyclic LDPC Decoder

Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. The decoder implementation complexity has been the bottleneck of its application. This paper presents an implementation of Quasi-Cyclic Low-Density Parity-Check decoder by using FPGA. Modified Min-Sum decoding algorithm is applied to reduce the memor...

Practical Encoder and Decoder for Power Constrained QC-LDPC lattices

LDPC lattices were the first family of lattices that equipped with iterative decoding algorithms under which they perform very well in high dimensions. In this paper, we introduce quasi cyclic low density parity check (QC-LDPC) lattices as a special case of LDPC lattices with one binary QC-LDPC code as their underlying code. These lattices are obtained from Construction A of lattices providing ...

On the Grobner Basis of a Family of Quasi-Cyclic LDPC Codes